AI–Hardware Co-Design: Advancing Quality, Productivity, and Reliability

Speaker:  Deming Chen – Urbana, USA
Topic(s):  Artificial Intelligence, Machine Learning, Computer Vision, Natural language processing , Graphics and Computer-Aided Design , Hardware, Power and Energy , Architecture, Embedded Systems and Electronics, Robotics , Computational Theory, Algorithms and Mathematics

Abstract

AI workloads, from edge intelligence to large language models (LLMs), are placing unprecedented demands on computing systems, exposing fundamental challenges in efficiency, productivity, and reliability, making AI–hardware (AI–HW) co-design essential. This talk presents a unified view of AI–HW co-design across models, compilers, architectures, and systems, demonstrating how coupling AI algorithms with hardware specialization reshapes performance, energy efficiency, and system robustness. It highlights the A3C3 (AI Algorithm–Accelerator Co-design, Co-search, and Co-generation) methodology, realized through FPGA- and GPU-based systems such as SkyNet, a co-designed model that won double championships at DAC 2019, and extends these principles to LLMs through works like Medusa, SnapKV, and StreamTensor for improved latency and energy efficiency. It further explores reliability through Proof2Silicon, integrating LLMs, formal verification, and hardware synthesis to bridge natural language specifications and silicon implementations. Together, these efforts illustrate how end-to-end AI–HW co-design provides a scalable framework for advancing quality, productivity, and reliability in next-generation AI systems.

About this Lecture

Number of Slides:  61
Duration:  50 min + 10 min Q&A minutes
Languages Available:  English
Last Updated:  08/04/2026

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